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No. 57 (1999/03) >

Title :4値VTゲート回路網の合成
Title alternative :Synthesis of Quaternary VT-gate Networks
Authors :比嘉, 広和
瑞慶覧, 長定
島袋, 勝彦
Authors alternative :Higa, Hirokazu
Zukeran, Chotei
Shimabukuro, Katsuhiko
Issue Date :Mar-1999
Abstract :Recently one of the most important problems is the pin limitations in the integrated circuits. Multiplevalued logic has attracted for solution of the problem. because for the same amount of information transfer, the total number of pins required in the multiple-valued integrated circuit chip is much less than that of an binary integrated. In this paper, we discuss synthesizing quaternary VT-gate networks. (VT-gate has variable threshold) An implicant in the function plays important role when synthesizing VT-gate networks. Because we can reduce the number of VT-gates in the networks by utilizing implicant. We apply a candidate for implicant in eval function and show good result was obtained.
Type Local :紀要論文
ISSN :0389-102X
Publisher :琉球大学工学部
URI :http://hdl.handle.net/20.500.12000/14148
Citation :琉球大学工学部紀要 no.57 p.59 -63
Appears in Collections:No. 57 (1999/03)

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